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document order number: mc34710 rev. 3.0, 3/2006 freescale semiconductor technical data * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2006. all rights reserved. dual output dc-dc & linear regulator ic the 34710 is a dual-output power regulator ic integrating switching regulator, linear regula tor, supervisory and power supply sequencing circuitry. with a wide operating input voltage range of 13 v to 32 v, the 34710 is applicable to many commercial and industrial applications using embedded mcus. a mode-selected 5.0 v or 3.3 v dc-dc switching regulator is provided for board-level i/o and user circuitry up to 700 ma. a linear regulator provides mode-selected core supply voltages of either 3.3v, 2.5v, 1.8v, or 1.5v at currents up to 500 ma. the supervisor circuitry ensures t hat the regulator outputs follow a predetermined power-up and power-down sequence. features ? efficient 5.0 v / 3.3 v buck regulator ? low noise ldo regulator (mode-selected 3.3v, 2.5v,1.8v, or 1.5v) ? on-chip thermal shutdown circuitry ? supervisory functions (power-on reset and error reset circuitry) ? sequenced i/o and core voltages ? pb-free packaging designated by suffix code ew figure 1. 34710 simplified application diagram dual output dc-dc & linear regulator dw suffix ew suffix (pb-free) 98asa10627d 32-terminal soicw 33710 ordering information device temperature range (t a ) package *pc33 710ew / r2 -40c to 105 32 soicw-ep mc34710ew/r2 0c to 85c 32 soicw-ep 34710 *device in development. electrical parameters being defined. mcu 34710 vswitch vfb linb + vcore vb rst gnd cp1 mode0 mode1 mode2 cp2 b+ 13 v to 32 v v i/o v core ct vi/o
analog integrated circuit device data 2 freescale semiconductor 34710 internal block diagram internal block diagram figure 2. 34710 simplifi ed internal block diagram charge 200 khz oscillator pump supervisory and temperature shutdown bandgap switching regulator v core linear regulator cp1 cp2 vb rst ct vfb vswitch vcore mode0 mode1 mode2 linb+ b+ gnd v i/o
analog integrated circuit device data freescale semiconductor 3 34710 terminal connections terminal connections figure 3. 34710 terminal connections table 1. 34710 termina l definitions terminal number terminal name terminal function formal name definition 1 rst reset reset reset is an open drain output only. 2 3 4 mode0 mode1 mode2 input mode control these input terminals control v fb and v core output voltages. 5 C 12, 14 C22, 24 nc nc no connects no internal connection to this terminal. 13 gnd ground ground ground. 23 vcore output core voltage regulator output core regulator output voltage. 25 linb+ input core voltage regulator input core regulator input voltage. 26 vfb input v i/o switching regulator feedback feedback terminal for v i/o switching regulator and internal logic supply. 27 vswitch output v i/o switching regulator switch output v i/o switching regulator switching output. 28 b+ input power supply input regulator input voltage. 29 vb output boost voltage boost voltage storage node. 30 cp2 passive component cp capacitor positive charge pump capacitor connection 2. 31 cp1 passive component cp capacitor negative charge pump capacitor connection 1. 32 ct passive component reset delay capacitor reset delay adjustment capacitor. 1 8 9 10 11 12 13 14 15 16 3 4 5 6 7 2 32 25 24 23 22 21 20 19 18 17 30 29 28 27 26 31 ct cp1 cp2 vb b+ vswitch vfb linb+ n/c vcore n/c n/c n/c n/c n/c n/c rst mode0 mode1 mode2 n/c n/c n/c n/c n/c n/c n/c n/c gnd n/c n/c n/c
analog integrated circuit device data 4 freescale semiconductor 34710 maximum ratings maximum ratings maximum ratings all voltages are with respect to ground un less otherwise noted. exceeding these ratings may cause a malfunction or permanent damage to the device. rating symbol max unit electrical ratings input power supply voltage i b + = 0.0 a v b + -0.3 to 36 v terminal soldering temperature (1) t solder 260 c power dissipation (2) p d 3.0 w esd standoff voltage non-operating, unbiased, human body model (3) v esd1 2000 v thermal resistance junction-to-ambient (4) junction-to-ambient (2) junction-to-exposed-pad r ja r ja r jc 45 25 2.0 c/w thermal ratings operating ambient temperature t a 0 to 85 c operating junction temperature t j 0 to 105 c input power supply voltage i b + = 0.0 a to 3.0 a v b + 13 to 32 v quiescent bias current from b+ (5) v b + = 13 v to 32 v i b+ ( q ) 7.5 ma v i /o switching regulator (6) maximum output voltage startup overshoot (c out = 330 f) mode0 = 0 mode0 = open v i / o ( startup ) 5.4 3.6 v maximum output current t a = 0c to 105c i vi/o 700 ma notes 1. soldering temperature limit is for 10 seconds maximum duration. not designed for imme rsion soldering. exc eeding these limits may cause malfunction or permanent damage to the device. 2. with 2.0 in 2 of copper heatsink. 3. e sd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ? ). 4. with no additional heatsinking. 5. maximum quiescent power dissipation is 0.25 w. 6. 13 v v b+ 32 v and - 20 c t j 145 c unless otherwise noted .
analog integrated circuit device data freescale semiconductor 5 34710 maximum ratings v core linear regulator (7) maximum output voltage startup overshoot (c out = 10 f) (8) mode2=low, mode1=low, mode0=low mode2=open, mode1=low, mode0=dont care mode2=low, mode1=open, mode0=dont care mode2=open, mode1=open, mode0=dont care v core ( startup ) 3.6 2.7 2.0 1.65 v maximum output current t j = 0c to 105c, v linb + v core (nom) + 0.8 v (9) i vcore 500 ma notes 7. 13 v v b+ 32 v and - 20 c t j 145 c unless otherwise noted . 8. refer to table 2 , page 9 . 9. pulse testing with low duty cycle used. maximum ratings (continued) all voltages are with respect to ground un less otherwise noted. exceeding these ratings may cause a malfunction or permanent damage to the device. rating symbol max unit
analog integrated circuit device data 6 freescale semiconductor 34710 static electrical characteristics static electrical characteristics static electrical characteristics characteristics noted under conditions 4.75 v v io 5.25 v, 13 v v b + 32 v, and 0 c t j 105 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit switching regulator (vi/o, mode0) logic supply voltage (i vi/o = 25 to 700 ma) mode0 = 0 mode0 = open (floating) v i / o 4.8 3.15 5.0 3.25 5.2 3.45 v output on resistance v b + = 13 v to 32 v r ds(on) 0.5 1.0 2.0 ? soft start threshold voltage mode0 = any v i / o ( soft ) C 2.5 3.1 v current limit threshold (t j = 25 c to 100 c) normal operation soft start, v i / o 2.5 v i limit ( op ) i limit ( soft ) 1.9 1.0 2.4 C 2.9 1.9 a minimum voltage allowable on v switch terminal t j = 25 c to 100 c v vswitch ( min ) -0.5 C C v linear regulator (vcore, mode 1, 2, 3, 4) supply voltage (i vcore = 5.0 ma) (10) mode2=low, mode1=dont care, mode0=low mode2=low, mode1=dont care, mode0=open mode2=open, mode1=dont care, mode0=low mode2=open, mode1=dont care, mode0=open v core ( nom ) 3.15 2.45 1.7 1.425 3.3 2.5 1.8 1.5 3.45 2.75 2.05 1.575 v supply voltage (i vcore = 500 ma) (10) mode2=low, mode1=dont care, mode0=low mode2=low, mode1=dont care, mode0=open mode2=open, mode1=dont care, mode0=low mode2=open, mode1=dont care, mode0=open v core ( nom ) 3.0 2.2 1.55 1.33 C C C C 3.4 2.6 1.9 1.53 v v core dropout voltage v core = v core ( nom ), i vcore = 0.5 a i vcore ( dropout ) C 0.5 0.8 v normal current limit threshold t j = 25c to 100c, v linb + = v core ( nom ) + 1.0 v i limit 600 800 1000 ma notes 10. refer to table 2 , page 9 .
analog integrated circuit device data freescale semiconductor 7 34710 static electrical characteristics mode terminals operating voltages mode control terminals low voltage v il ( mode n ) C C 0.825 v mode control terminals high voltage v ih ( mode n ) 2.6 C C v mode control terminals voltage with input floating v b + = 13 v to 14 v v mode ( float ) 7.0 8.0 13 v supervisor circuitry ( rst , vcore) minimum function v b + for charge pump and oscillator running v b + ( min ) C C 9.0 v minimum v b + for rst assertion, v b + rising v b+ ( assert ) C 1.9 2.2 v rst low voltage v b + = 2.0 v, i rst 5.0 ma v ol C 0.25 0.4 v rst v i / o threshold v i / o rising v i / o falling v i / o t + v i / o t - C v i/o ( nom ) - 300 mv C C v i/o ( nom ) - 50 mv C v rst hysteresis for v i / o v hysvi/o 10 C 100 mv rst v core threshold v core rising v core falling v coret + v core t - C v core ( nom ) - 300 mv C C v core ( nom ) - 30 mv C v rst hysteresis for v core v b + = 13 v to 32 v v hys core 10 50 100 mv v core - v i / o for v core shutdown v b + = 13 v to 32 v v core ( shutdown ) 0.5 C 0.9 v thermal shutdown temperature t j rising t j ( tsd ) C C 170 c overtemperature hysteresis t j ( hysteresis ) C 20 C c vb charge pump boost voltage (11) v b + = 12 v, i vb = 0.5 ma v b + = 32 v, i vb = 0.5 ma v b v b v b + 8 v b + 10 v b + 9 v b + 12 v b + 10 v b + 14 v notes 11. bulk capacitor esr 10 milliohms static electrical charac teristics (continued) characteristics noted under conditions 4.75 v v io 5.25 v, 13 v v b + 32 v, and 0 c t j 105 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 8 freescale semiconductor 34710 dynamic electrical characteristics dynamic electrical characteristics dynamic electrical characteristics characteristics noted under conditions 4.75 v v io 5.25 v, 13 v v b + 32 v, and 0 c t j 105 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted characteristic symbol min typ max unit v i /o switching regulator duty cycle d 45 49 55 % switching rise and fall time load resistance = 100 ? , v b + = 30 v t r , t f 20 35 50 ns supervisor circuitry (rst) rst delay c delay = 0.1 f t delay 40 60 80 ms rst filter time v b + = 9.0 v t filter 2.0 4.0 8.0 s rst fall time c l = 100 pf, r pullup = 4.7 k ? , 90% to 10% t f C 25 75 ns c delay charge current threshold voltage i cdly v thcd 2.0 1.7 3.5 2.0 5.0 2.2 a v internal oscillator charge pump and v i / o switching regulator operating frequency v b + = 12 v to 32 v f op 140 170 260 khz
analog integrated circuit device data freescale semiconductor 9 34710 functional description introduction functional description introduction v i /o switching regulator the v i /o switching regulator output voltage is determined by the mode digital input terminals. the 34710s mode terminals select the output volt age. for example, if mode2, mode1, and mode0 are set to 0, 0, 0 (respectively) then v i /o will be set to 5.0 v; if mode2, mode1, and mode0 are all left floating (i.e., open, open, and open), then the voltage for v i /o will be set to 3.3 v. table 2 provides the truth table for setting the various combination of regulator outputs via the mode pins. the topology of the regulator is a hysteretic buck regulator operating from the internal ~200 khz oscillator. v core linear regulator the v core linear ldo (low drop-out) regulator can produce either a +3.3 v, 2.5 v, 1.8 v, or 1.5 v output voltage at currents up to 500 ma. the input to the vcore regulator is a terminal that may be connected to the v i /o regulator output or to an external power supply. note, the minimum input voltage level must be equal to or greater than the selected v core voltage + 0.8 v. (i.e., 0.8v is the ldo regulator drop out voltage.) the mode terminals select the output voltage as depicted in table 2 . functional terminal description power supply input (b+) main supply voltage for the v i/o switching regulator and general chip bias circuitry. core voltage regulator input (lin b+) supply voltage for the v core regulator. may be provided by the v i/o regulator output or from an independent supply. mode control (mode 0,1,2) mode select terminals to select the v i/o and v core output voltages per table 2. pull to ground for low state, float for high state. switching capacitors 1 and 2 (cp1/cp2) terminals for the charge pump capacitor. boost voltage (vb) the boost voltage is an output terminal used for the charge pump boost voltage and is a connection point for the charge pump bulk capacitor.it provides a gate drive for the v i/o switch fet. reset ( r st ) reset is an output terminal for supervisory functions. this terminal is in high state during normal operation and low state during fault conditions. this terminal has no input function and requires an external pull-up resistor. the rst terminal is an open drain output driver to prevent oscillations during the transition. it is recommended to connect a 0.1 uf capacitor between the ct pin and rst pin. note: error conditions must be present for a minimum time, t filter , before the 34710 responds to them. once all error conditions have been cleared, rst is held low for an additional time of t delay . reset delay capacitor (ct) this terminal is the external delay. it is used with a capacitor to ground to delay r st turn-on time and to r st to prevent r st oscillations during chip power-on. vi/o switching regulator feedback (vfb) this terminal is the feedback input for the v i/o switching regulator and the output of the regulator application. vi/o switching regulator output (vswitch) this terminal is the switching output for the v i/o buck regulator. it has internal high side fet. table 2. v i /o and v core regulator output voltage selection mode2 mode1 mode0 v i /o (v) v core (v) 0005.0 3.3 0 0 open 3.3 2.5 0 open 0 5.0 1.8 0 open open 3.3 1.8 open 0 0 5.0 2.5 open 0 open 3.3 2.5 open open 0 5.0 1.5 open open open 3.3 1.5 open indicates terminal is not c onnected externally (i.e. floating).
analog integrated circuit device data 10 freescale semiconductor 34710 functional description functional terminal description supervisory functions supervisory circuitry the supervisory circuitry provides control of the rst line, an open drain signal, based on system operating conditions monitored by the 34710. v i /o , v core , v b+ , and thermal shutdown (tsd) detectors in va rious parts of the chip are monitored for error conditions. v i /o , v core , v b+ , and thermal shutdown have both positive- and negative-going thresholds for triggering the reset function. the supervisor circuitry also ensures that the regulator outputs follow a predetermined power-up and power-down sequence. specific ally, the sequencing ensures that v i /o is never less than 0.9 v below v core . this means that v core - v i /o will be clamped at 0.5 v, and that the v core regulator operation will be suppressed during startup and shutdown to ensure that v core - v i /o = 0.9 v. vb charge pump the high-side mosfet in the switching regulator (buck converter) requires a gate drive supply voltage that is biased higher than the b+ voltage, an d this boosted voltage is provided by the internal charge pump and stored in a capacitor between the vb pin and the b+ pin. the charge pump operates directly from the b+ supply, and uses an internal oscillator operating at 200 khz. internal oscillator the internal oscillator provides a 200 khz square wave signal for charge pump operation and for the buck converter.
analog integrated circuit device data freescale semiconductor 11 34710 typical applications typical applications figure 4. typical application diagram the mc34710 provides both a buck converter and an ldo regulator in one ic. figure 4 above shows a typical application schematic for the mc34710. l1 is the buck converter's inductor. the buck inductor is a key component and must not only present the re quired reactance, but do so at a dc resistance of less than 20 milliohms in order to preserve the converter's efficiency. also important to the converter's efficiency is the utilization of a low vf schottky diode for d1. note that a 0.1uf capacitor is connected between ct and the reset pins; this prevents any possibility of oscillations occurring on the reset line during transitions by allowing the ct terminal to discharge to ground potential via the rst pin, and then charge when rst returns to a logic high. the capacitor between the cp1 a nd cp2 pins is the charge pump's bucket capacitor, and sequentially charges and discharges to pump up the reservoir capacitor connected to the vb pin. note that the reservoir capacitor's cathode is connected to b+ rather than ground. also note that the charge pump is intended only to provide gate-drive potential for the buck regulator's internal power mosfet, and therefore connecting external loads to the vb pin is not recommended. the ic's internal v core ldo regulator can provide up to 500 ma of current as long as the operating junction temperature is maintained below 105 degrees c. the heat- generating power dissipation of the ldo is primarily a function of the volt x amp pr oduct across the linb+ and vcore terminals. therefore, if the linb+ voltage is >> than the selected v core voltage + 0.8 v, it is recommended to use a power resistor in series wit h the linb+ input to drop the voltage and dissipate the heat externally from the ic. for example, if the output of the buck regulator (v i/o on the schematic) is used as the input to linb+, and the mode switches are set such that v i/o = 5 v and v core = 3.3 v, then a series resistance of 1.8 ohms at the linb+ pin would provide an external voltage drop at 500 ma while still leaving the minimum required headroom of 0.8 v. conversely, if the mode switches are set such that v i/o = 3.3 v and v core = 2.5 v, then no series resistance would be required, even at the maximum output current of 500 ma. designing a power supply circuit with the mc34710, like all dc-dc converter ics, requires special attention not only to component selection, but also to component placement (i.e., printed circuit board layout). the mc34710 has a nominal switching frequency of 200 khz, and therefore pcb traces between the buck converter discrete component terminals and the ic should be kept as short and wide as possible to keep the parasitic inductance lo w. likewise, keeping these ldo 1 2 3 4 13 23 24 25 26 27 28 29 30 31 32 b+ 13 v - 32 v rst mode0 mode1 mode2 gnd ct cp1 cp2 vb b+ vsw vfb linb vcore supervisory & shutdown buck reg charge pump c1 330 f r1 1 k c1 0.1 mf c5 0.1 f c6 10 f rseries 1.8 330 f c8 1 2 v i/o v core sw1 d1 mbrs130lt3 mc34710 100 h l1
analog integrated circuit device data 12 freescale semiconductor 34710 typical applications pcb traces short and wide helps prevent the converter's high di/dt switching transients from causing emi/rfi. figure 5. typical pcb layout figure 5 shows a typical layout for the pcb traces connecting the ic's switching terminal (vswitch) and the power inductor, rectifier, and filter components. also, it is recommended to design the component layout so that the switching currents can be immediately sunk into a broad full-plane ground that provides terminations physically right at the corresponding component leads. this helps prevent switching noise from pr opagating into other sections of the circuitry. figure 6. bottom copper layout figure 6 illustrates a pcb typical bottom copper layout for the area underneath a buck conv erter populated on the top of the same section of pcb. the ground plane is highlighted so the reader may note how the ground plane has been kept as broad and wide as possible. the square vias in the plane are located to provide an immediate path to ground from the top copper circuitry. figure 7. top copper layout figure 7 shows the corresponding top copper circuit area with the component placement. again, the ground plane and the vias have been highlighted so the reader may note the proximity of these current sink pathways to the key converter components. it is also important to keep the power planes of the switching converter's output spread as broad as possible beneath the passive components, as this helps reduce emi/rfi and the potential for coupling noise transients into adjacent circuitry. figure 8. output plane of buck converter figure 8 shows the output plane of the buck converter highlighted.
analog integrated circuit device data freescale semiconductor 13 34710 typical applications this layout provides the lowest possible impedance as well as lowest possible dc resistance for the power routing. note that the power path and its return should be placed, if possible, on top of each other on different layers or opposite sides of the pcb. small ceramic capacitors are placed in parallel with the aluminum electrolytics so that the overall bulk filtering presents a low esl to the high di/dt switching currents. alternatively, special low esl/esr switching-grade electrolytics may be used. an additional feature of the mc34710 is the 32 soicw-ep exposed pad package. the package allows heat to be conducted from the die down through the exposed metal pad underneath the package and into the copper of the pcb. in order to best take advantage of this feature, a grid array of thru-hole vias should be placed in the area corresponding to the exposed pad, and these vias then should then connect to a large ground plane of copper to dissipate the heat into the ambient environment. an exampl e of these vias can be seen in the previous figures of a typical pcb layout.
analog integrated circuit device data 14 freescale semiconductor 34710 packaging package dimensions packaging package dimensions ew (pb-free) suffix 32-lead soicw-exposed pad plastic package 98asa10627d issue o
analog integrated circuit device data freescale semiconductor 15 34710 packaging package dimensions ew (pb-free) suffix 32-lead soicw-exposed pad plastic package 98asa10627d issue o
analog integrated circuit device data 16 freescale semiconductor 34710 revision history revision history revision date description of changes 2.0 3/2006 ? converted to freescale format ? updated maximum ratings, static and dynamic characteristics tables. ? updated packaging drawing ? changed terminal vi/o_out to vfb ? implemented revision history page 3.0 3/2006 ? updated format from preliminary to advance information. ? format and style corrections to match standard template.
mc34710 rev. 3.0 3/2006 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescales environmental products program, go to http:// www.freescale.com/epp . information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. typical parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals, must be validated for each customer application by customers technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2006. all rights reserved.

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